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HP4410DY
Data Sheet December 2001
10A, 30V, 0.0135 Ohm, Single N-Channel, Logic Level Power MOSFET
This power MOSFET is manufactured using an innovative process. This advanced process technology achieves the lowest possible on-resistance per silicon area, resulting in outstanding performance. This device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge. It was designed for use in applications where power efficiency is important, such as switching regulators, switching converters, motor drivers, relay drivers, lowvoltage bus switches, and power management in portable and battery-operated products.
Features
* Logic Level Gate Drive * 10A, 30V * rDS(ON) = 0.0135 at ID = 10A, VGS = 10V * rDS(ON) = 0.020 at ID = 8A, VGS = 4.5V * Related Literature - TB334, "Guidelines for Soldering Surface Mount Components to PC Boards"
Symbol
Ordering Information
PART NUMBER HP4410DY PACKAGE SO-8 BRAND P4410DY
SOURCE(1)
DRAIN(8)
SOURCE(2)
DRAIN(7)
NOTE: When ordering, use the entire part number. Add the suffix T to obtain the variant in tape and reel, e.g., HP4410DYT.
SOURCE(3) DRAIN(6)
GATE(4)
DRAIN(5)
Packaging
SO-8
(c)2001 Fairchild Semiconductor Corporation
HP4410DY Rev. B
HP4410DY
Absolute Maximum Ratings
TA = 25oC, Unless Otherwise Specified HP4410DY Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (10s Pulse Width) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 30 30 16 10 50 2.5 0.02 -55 to 150 300 260 UNITS V V V A A W W/oC
oC oC oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. TA = 25oC to 125oC.
Electrical Specifications
PARAMETER
TA = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS TEST CONDITIONS ID = 250A, VGS = 0V VGS = VDS, ID = 250A (Figure 9) VDS = 30V, VGS = 0V VDS = 30V, VGS = 0V, TA = 55oC MIN 30 1 VDS = 15V, VGS = 10V, ID 10A VDS = 25V, VGS = 0V, f = 1MHz (Figure 4) Pulse Width < 10s (Figure 11) Device Mounted on FR-4 Material TYP 0.015 0.011 15 9 70 20 35 7.5 5.8 1600 685 115 MAX 1 25 100 0.020 0.0135 30 20 100 80 60 50 UNITS V V A A nA ns ns ns ns nC nC nC pF pF pF
oC/W
Drain to Source Breakdown Voltage Gate to Source Threshold Voltage Zero Gate Voltage Drain Current
Gate to Source Leakage Current Drain to Source On Resistance
IGSS rDS(ON)
VGS = 16V ID = 8A, VGS = 4.5V (Figures 6, 8) ID = 10A, VGS = 10V (Figures 6, 8)
Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge Gate to Source Charge Gate to Drain Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance Junction to Ambient
td(ON) tr td(OFF) tf Qg(TOT) Qgs Qgd CISS COSS CRSS RJA
VDD = 25V, ID 1A, RL = 25, VGEN = 10V, RGS = 6
Source to Drain Diode Specifications
PARAMETER Source to Drain Diode Voltage Reverse Recovery Time SYMBOL VSD trr TEST CONDITIONS ISD = 2.3A (Figure 7) ISD = 2.3A, dISD/dt = 100A/s MIN TYP 0.75 50 MAX 1.1 80 UNITS V ns
(c)2001 Fairchild Semiconductor Corporation
HP4410DY Rev. B
HP4410DY Typical Performance Curves
50 VGS = 10V - 5V 4V ID, DRAIN CURRENT (A)
Unless Otherwise Specified
50 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 40 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX
ID, DRAIN CURRENT (A)
40
30 3V 20
30
20
10
10
TA = 125oC
-55oC 25oC
0 0 2 4 6 8 10 VDS, DRAIN TO SOURCE VOLTAGE (V)
0 0 1 2
3
4
5
VGS, GATE TO SOURCE VOLTAGE (V)
FIGURE 1. OUTPUT CHARACTERISTICS
FIGURE 2. TRANSFER CHARACTERISTICS
0.030 0.025 0.020 VGS = 4.5V 0.015 0.010 0.005 0 0 10 20 30 40 50 ID, DRAIN CURRENT (A) VGS = 10V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX C, CAPACITANCE (pF)
4200 3500 2800 2100 1400 COSS 700 0 0 6 12 18 24 VDS , DRAIN TO SOURCE VOLTAGE (V) 30 CRSS VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS = CDS + CGD
rDS(ON), DRAIN TO SOURCE
ON STATE RESISTANCE (W)
CISS
FIGURE 3. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT
FIGURE 4.
CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
10 VGS , GATE TO SOURCE VOLTAGE (V) NORMALIZED DRAIN TO SOURCE ON RESISTANCE VDS = 15V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX ID = 10A 8
2.0 VGS = DURATION = 80s PULSE 10V DUTY CYCLE = 0.5% MAX ID = 10A 1.5
6
1.0
4
2
0.5
0 0 9 18 27 36 45 Qg, GATE CHARGE (nC)
0 -50
-25
0 25 50 75 100 TJ, JUNCTION TEMPERATURE (oC)
125
150
FIGURE 5.
GATE TO SOURCE VOLTAGE vs GATE CHARGE
FIGURE 6. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
(c)2001 Fairchild Semiconductor Corporation
HP4410DY Rev. B
HP4410DY Typical Performance Curves
50 ISD, SOURCE TO DRAIN CURRENT (A) PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TJ = 150oC 10 TJ = 25oC
Unless Otherwise Specified (Continued)
0.10 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX
rDS(ON), DRAIN TO SOURCE
ON STATE RESISTANCE (W)
0.08
0.06 ID = 10A 0.04
0.02
1 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 VSD, SOURCE TO DRAIN VOLTAGE (V)
0 0 2 4 6 8 10 VGS, GATE TO SOURCE VOLTAGE (V)
FIGURE 7. SOURCE TO DRAIN DIODE VOLTAGE
FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE TO SOURCE VOLTAGE
0.4 0.2 VGS(TH) VARIANCE (V)
80
60 0.0 ID = 250A -0.2 -0.4 -0.6 -0.8 -50 -25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (oC) 0 0.01 POWER (W)
40
20
0.10
1.00 t, PULSE WIDTH (s)
10.00
FIGURE 9. GATE THRESHOLD VOLTAGE VARIANCE vs JUNCTION TEMPERATURE
FIGURE 10. SINGLE PULSE POWER CAPABILITY vs PULSE WIDTH
2 1 DUTY CYCLE = 0.5 THERMAL IMPEDANCE ZJA, NORMALIZED 0.2 0.1 0.1 0.05 0.02 SINGLE PULSE 0.01 10-4 10-3 10-2 10-1 1 t1 t2 DUTY CYCLE, D = t1/t2 TJ = PD x ZJA x RJA + TA SURFACE MOUNTED 10 30 PDM
t, RECTANGULAR PULSE DURATION (s)
FIGURE 11. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
(c)2001 Fairchild Semiconductor Corporation
HP4410DY Rev. B
HP4410DY Test Circuits and Waveforms
VDS tON td(ON) RL VDS
+
tOFF td(OFF) tr tf 90%
90%
VGS
DUT RGS
VDD 0
10% 90%
10%
VGS VGS 0 10%
50% PULSE WIDTH
50%
FIGURE 12. SWITCHING TIME TEST CIRCUIT
FIGURE 13. SWITCHING TIME WAVEFORM
VDS RL
VDD Qg Qgd Qgs VGS
VGS
+
VDD DUT Ig(REF) Ig(REF) 0 0
VDS
FIGURE 14. GATE CHARGE TEST CIRCUIT
FIGURE 15. GATE CHARGE WsAVEFORMS
(c)2001 Fairchild Semiconductor Corporation
HP4410DY Rev. B
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
ACExTM BottomlessTM CoolFETTM CROSSVOLTTM DenseTrenchTM DOMETM EcoSPARKTM E2CMOSTM EnSignaTM FACTTM FACT Quiet SeriesTM
DISCLAIMER
FAST (R) FASTrTM FRFETTM GlobalOptoisolatorTM GTOTM HiSeCTM ISOPLANARTM LittleFETTM MicroFETTM MicroPakTM MICROWIRETM
OPTOLOGICTM OPTOPLANARTM PACMANTM POPTM Power247TM PowerTrench (R) QFETTM QSTM QT OptoelectronicsTM Quiet SeriesTM SILENT SWITCHER (R)
SMART STARTTM STAR*POWERTM StealthTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogicTM TruTranslationTM UHCTM UltraFET (R)
VCXTM
STAR*POWER is used under license
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant into support device or system whose failure to perform can the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Rev. H4

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